Common hardware-in-the-loop development

被引：0
|
作者：
Kim, Hajin J. [1 ]
Moss, Stephen G. [2 ]
机构：
[1] USA, RDECOM, Aviat & Missile RDEC, RDMR SSE H, Bldg 5400, Redstone Arsenal, AL 35898 USA
[2] AEgis Technol Grp Inc, Huntsville, AL 35806 USA
来源：
TECHNOLOGIES FOR SYNTHETIC ENVIRONMENTS: HARDWARE-IN-THE-LOOP TESTING XV | 2010年 / 7663卷
关键词：
hardware-in-the-loop; network; architecture; latency; FPGA; modular; interface;
D O I：
10.1117/12.852449
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An approach to streamline the Hardware-In-the-Loop (HWIL) simulation development process is under evaluation. This Common HWIL technique will attempt to provide a more flexible, scalable system. The overall goal of the Common HWIL system will be to reduce cost by minimizing redundant development, operational labor and equipment expense. This paper will present current results and future plans of the development.
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页数：11
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