Multi-gate CMOS with fin-channel structures beyond planar CMOS scaling limits

被引：0
|
作者：
Hisamoto, D [1 ]
机构：
[1] Hitachi Ltd, Cent Res Lab, Tokyo 1858601, Japan
来源：
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A great deal of attention has been paid to FD-SOI and multi-gate devices because they show promise in overcoming device scaling limits. Here, many reported types of fin-channel devices are reviewed regarding their potential as technology boosters for post-CMOS scaling. This paper demonstrates that double-, triple-, and quadruple-gates have different advantages. Therefore, the device structure should be individually designed accordingly for specific applications.
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页码：96 / 99
页数：4
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