Physics-based surface potential, electric field and drain current model of a p+ Si1-xGex gate-drain underlap nanoscale n-TFET

被引:19
|
作者
Goswami, Rupam [1 ]
Bhowmick, Brinda [1 ]
Baishya, Srimanta [1 ]
机构
[1] Natl Inst Technol, Dept Elect & Commun Engn, Silchar 788010, Assam, India
关键词
Tunnel FET; band-to-band tunnelling; Poisson's equation; surface potential; electric field; TUNNEL FET; EFFECT TRANSISTORS; MOSFETS; PERFORMANCE; SOI;
D O I
10.1080/00207217.2016.1138514
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article develops a 2-D model for surface potential, electric field and drain current for a nanoscale silicon tunnel field effect transistors (TFET) with a delta p(+)Si(1-x)Ge(x) layer at source-channel tunnel junction. Mathematical formulation based on the TFET physics has been carried out throughout the text taking into consideration the various parameters involving the mole-fraction-dependent Si1-xGex layer. Both lateral and vertical electric fields have been modelled. A comparison is conducted between the modelled and the simulated values for three cases: polysilicon gate with silicon dioxide as gate dielectric, aluminium gate with alumina as gate dielectric and aluminium gate with hafnium oxide as gate dielectric. The model is found to be valid for all the three cases.
引用
收藏
页码:1566 / 1579
页数:14
相关论文
共 12 条
  • [1] Hetero-Gate-Dielectric Gate-Drain Underlap Nanoscale TFET with a δp+ Si1-xGex Layer at Source-Channel Tunnel Junction
    Goswami, Rupam
    Bhowmick, Brinda
    [J]. 2014 INTERNATIONAL CONFERENCE ON GREEN COMPUTING COMMUNICATION AND ELECTRICAL ENGINEERING (ICGCCEE), 2014,
  • [2] A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement*
    Thakur, Anchal
    Dhiman, Rohit
    [J]. MICROELECTRONICS JOURNAL, 2022, 126
  • [3] Influence of the highly-doped drain implantation and the window size on defect creation in p+/n Si1-xGex Source/Drain junctions
    Chowdhury, M. Kamruzzaman
    Vissouvanadin, B.
    Gonzalez, M. Bargallo
    Bhouri, N.
    Verheyen, P.
    Hikavyy, A.
    Richard, O.
    Geypen, J.
    Bender, H.
    Loo, R.
    Claeys, C.
    Simoen, E.
    Machkaoutsan, V.
    Tomasini, P.
    Thomas, S. G.
    Lu, J. P.
    Weijtmans, J. W.
    Wise, R.
    [J]. GETTERING AND DEFECT ENGINEERING IN SEMICONDUCTOR TECHNOLOGY XII, 2008, 131-133 : 95 - +
  • [4] Drain current model for strained-Si/Si1-xGex/strained-Si double-gate MOSFETs including quantum effects
    Mohammadi, S.
    Afzali-Kusha, A.
    Mohammadi, S.
    [J]. SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2011, 26 (09)
  • [5] Analytical surface potential based drain current model for nanoscale strained-Si/SiGe MOSFET
    Batwani, Himanshu
    Gaur, Mayank
    Kumar, M. Jagadesh
    [J]. PROCEEDINGS OF THE 2007 INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES: IWPSD-2007, 2007, : 212 - 216
  • [6] A physics-based potential and electric field model of a nanoscale rectangular high-K gate dielectric HEMT
    B DAS
    R GOSWAMI
    B BHOWMICK
    [J]. Pramana, 2016, 86 : 723 - 736
  • [7] A physics-based potential and electric field model of a nanoscale rectangular high-K gate dielectric HEMT
    Das, B.
    Goswami, R.
    Bhowmick, B.
    [J]. PRAMANA-JOURNAL OF PHYSICS, 2016, 86 (04): : 723 - 736
  • [8] Effect of Ge Mole Fraction on Current, Voltage and Electric Field Characteristics of High Doping Nanoscale Si1-xGex/Si P-N Diode
    Narottama, Anak Agung Ngurah Made
    Sapteka, Anak Agung Ngurah Gde
    [J]. 2017 15TH INTERNATIONAL CONFERENCE ON QUALITY IN RESEARCH (QIR) - INTERNATIONAL SYMPOSIUM ON ELECTRICAL AND COMPUTER ENGINEERING, 2017, : 57 - 60
  • [9] A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET
    Bhattacharjee, Abhishek
    Dasgupta, Sudeb
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (02) : 448 - 455
  • [10] Analytical drain current model of strained junctionless nanowire tunnel field-effect transistor fabricated on Si1-xGex virtual substrate
    Zhang, Yefei
    Li, Zunchao
    [J]. IET CIRCUITS DEVICES & SYSTEMS, 2020, 14 (08) : 1195 - 1200