Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power. A novel variable hysteresis Schmitt Trigger (ST) is used for external programmability. Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power. This architecture with reduced circuit complexity considerably improves the earlier realizations by eliminating multiple current sources as well switched capacitor circuits and results in power saving up to 87 %. Proposed PAM design demonstrates an improved SNDR of 115 dB, DR of 96 dB, and power consumption below 280 mu W. It illustrates Effective Number of Bits (ENOB) to 18.81 and Figure of Merit (FoM) to 0.15 fJ/conversion step. Modulator is implemented in Cadence UMC Hspice 0.18 mu m CMOS analog technology. Off-chip PAM control for resolution/power performance has potential applications in battery operated ultra low power applications like IoT; where ADC is one of the major power consuming components. It offers the promise for an efficient performance with power saving.