Rapid prototyping for configurable System-on-a-Chip platforms: A simulation based approach

被引：2

作者：

Bieger, J ^{[1
]}

Huss, SA ^{[1
]}

Jung, M ^{[1
]}

Klaus, S ^{[1
]}

Steininger, T ^{[1
]}

机构：

[1] Tech Univ Darmstadt, Dept Comp Sci, Integrated Circuits & Syst Lab, D-64283 Darmstadt, Germany

来源：

17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA | 2004年

关键词：

D O I：

10.1109/ICVD.2004.1260981

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemmingfrom requirements of the application and limitations of the architecture. In a topdown approach a real-time MPEG 1 Layer 3 (MP3) decoder is designed on this SoC, which integrates FPGA resources and an AVR microcontroller core within a single chip. An intensive design space exploration based on simulations on different levels of abstractions isfundamental for a real-time implementation on this limited architecture. After determining a suitedfunctional partitioning a special DSP is implemented on the FPGA, wherefore an instruction set simulator is build, which allows concurrent HW/SW development.

引用

页码：577 / 582

页数：6

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