A 25-28Gb/s PLL-based Full-Rate Reference-Less CDR in 0.13μm SiGe BiCMOS

被引：0

作者：

Zhang, Peng ^{[1
]}

Zhang, Changchun ^{[1
,2
]}

Zhang, Jingjian ^{[1
]}

Zhang, Yi ^{[1
]}

Zhang, Ying ^{[1
]}

Ji, Xincun ^{[1
]}

机构：

[1] Nanjing Univ Posts & Telecommun, Coll Elect Sci & Engn, Nanjing 210023, Jiangsu, Peoples R China

[2] Southeast Univ, State Key Lab Millimeter Waves, Nanjing 210096, Jiangsu, Peoples R China

来源：

2017 2ND IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM) | 2017年

关键词：

clock and data recovery; phase-locked loop; Bang-Bang PD; quadrature voltage control oscillator; DATA RECOVERY CIRCUIT; RATE CLOCK; DETECTOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 25-28Gb/s full-rate reference-less CDR is presented and designed in a standard 0.13 mu m SiGe BiCMOS process, which can be applicable to nearly all classical 100G communication protocols by multi-channel configuration. It consists mainly of a full-rate phase frequency detector, a quadrature voltage control oscillator and two voltage to current convertors with loop filters. A dual-loop topology is adopted in order for a wide frequency acquisition range and an excellent jitter performance. Simulation results show that the proposed CDR operates properly at a data rate of 2528Gb/s. When a 25Gb/s PRBS data is applied, the jitters of the recovered clock and data are 0.34ps and 2.8ps, respectively, with 91 mA current consumption from a single power supply of 1.7V.

引用

页码：186 / 190

页数：5

共 42 条

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