A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference

A dual-output CMOS voltage reference is presented for ultra-low power applications that require two or more different voltage references. The VREF1 is designed by employing the VTH difference between two devices to compensate the temperature coefficient (TC) of the thermal voltage. The VREF2 is generated by feeding a current mirrored from the first reference voltage's supply current into a diodeconnected-transistor load. In such a way, two different voltage references can be generated in one compact and simple design to reduce the devices and chip area significantly, compared to two separate voltage references in a conventional design. Fabricated in a 0.18-mu m CMOS process, the proposed CMOS voltage reference can provide two references of 331.8 and 660.3 mV with variation coefficients of 0.53% and 0.42%, respectively. The average TCs of V-REF1 and V-REF2 for a temperature range of -40 to 125. C are measured as 41.7 and 24.5 ppm/.C, respectively. The line sensitivity (LS) of V-REF1 is 0.0505 %/V with 0.6-1.8 V supply, and the LS of V-REF2 is 0.114 %/V with 0.8-1.8 V supply. The measured results show a competitive power supply ripple rejection, and the power consumption is only 4.12 nW with 0.8-V minimum supply at 25 degrees C, while the active area is 0.0108 mm(2).