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- [6] Bandwidth-Aware Test Compression Logic for SoC Designs 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
- [7] Race Logic Synthesis for A Multithreaded HDL/ESL Simulator for SoC Designs PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 1179 - 1182
- [8] An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2020, 36 (01): : 135 - 142
- [9] An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic Journal of Electronic Testing: Theory and Applications (JETTA), 2020, 36 (01): : 135 - 142
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