Adding reconfigurable logic to SOC designs

被引:0
|
作者
Gupta, B [1 ]
Parviainen, JA
Schaumont, P
Tanurhan, Y
Roy, K
机构
[1] STMicroelect, ST Berkeley Lab, Berkeley, CA USA
[2] Nokia Mibilke Phones, Baseband Res & Technol Dept, Oulu, Finland
[3] IMEC, Design Technol Integrated Informat & Commun Syst, Louvain, Belgium
[4] Actel, Enbedded FPGA Grp, Sunnyvale, CA USA
[5] Purdue Univ, W Lafayette, IN 47907 USA
来源
IEEE DESIGN & TEST OF COMPUTERS | 2001年 / 18卷 / 04期
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:65 / 71
页数:7
相关论文
共 50 条
  • [1] Adding reconfigurable logic to SOC designs
    IEEE Design and Test of Computers, 2001, 18 (04): : 65 - 71
  • [2] Reconfigurable logic in SoC systems
    Greenbaum, J
    PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2002, : 5 - 8
  • [3] Programmable logic challenges traditional ASIC SoC designs
    Bursky, Dave
    2002, Penton Publishing Co. (50)
  • [4] RaceCheck: A race logic audit program for SoC designs
    Chan, Terence
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 97 - 100
  • [5] A flexible logic BIST scheme and its application to SoC designs
    Wen, XQ
    Wang, HP
    10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 463 - 463
  • [6] Bandwidth-Aware Test Compression Logic for SoC Designs
    Janicki, Jakub
    Tyszer, Jerzy
    Mrugalski, Grzegorz
    Rajski, Janusz
    2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
  • [7] Race Logic Synthesis for A Multithreaded HDL/ESL Simulator for SoC Designs
    Chan, Terence
    PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 1179 - 1182
  • [8] An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic
    Patel, Sujit Kumar
    Garg, Bharat
    Rai, Shireesh Kumar
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2020, 36 (01): : 135 - 142
  • [9] An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic
    Patel, Sujit Kumar
    Garg, Bharat
    Rai, Shireesh Kumar
    Journal of Electronic Testing: Theory and Applications (JETTA), 2020, 36 (01): : 135 - 142
  • [10] An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic
    Sujit Kumar Patel
    Bharat Garg
    Shireesh Kumar Rai
    Journal of Electronic Testing, 2020, 36 : 135 - 142