A VLSI switch architecture for broadband satellite networks

被引：0
|
作者：
Wassal, AG [1 ]
Hasan, MA [1 ]
机构：
[1] Univ Waterloo, Dept Elect & Comp Engn, Waterloo, ON N2L 3G1, Canada
来源：
1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/MWSCAS.1998.759431
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper an ATM switch architecture is proposed for satellite on-board processing. The switch is based on a shared memory architecture for the switching fabric and a circular sorting queue for the buffer management unit. The design is constrained by both the network performance requirements and the limited payload of the satellite in terms of mass, area and power. A low-power ASIC implementation of the sorting queue that can support an aggregate traffic rare up to 21.2 Gbps is also presented.
引用
收藏
页码：42 / 45
页数：4
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