Fast Sequential FPGA Startup based on Partial and Dynamic Reconfiguration

Due to their their high flexibility and their increasing logic resources, FPGAs can be found in a wider application range as in recent years. But especially in application domains, where only a very restricted power budget is available, FPGAs still have to compete with other solutions. To reduce the power consumption to a minimum, many devices use different kinds of power saving modes, called sleep modes. In those modes they sacrifice functionality for the benefit of a lower consumption. Taking this idea to the extreme, many devices are only powered when it is necessary. If not, they are released from their power supply and do not drain current at all. The realization of such a sleep mode for a SRAM-based FPGA leads to difficulties. This is caused due to the fact, that the volatile memory is used to save the configuration of the device. The configuration has to be reloaded into the device every time when reattaching the power to the FPGA. This circumstance leads to restrictions for the device deployment in some electronic systems since in many cases the time a device may use to wake up is strictly limited. In several use cases, the configuration time of a SRAM based FPGA exceeds this limitation. This paper describes to decrease the configuration time of a design by exploiting the method of dynamic and partial reconfiguration in order to enable the usage of a sleep mode. With the presented method, the configuration time of any Xilinx SRAM based FPGA from the identical series (e.g. Spartan) is independent from the size of the used device.