Building a Dynamically Reconfigurable System Through a High Development Flow

被引:0
|
作者
de la Fuente, David [1 ]
Barba, Jesus [1 ]
Pena, Xerach [1 ]
Carlos Lopez, Juan [1 ]
Penil, Pablo [2 ]
Pedro Sanchez, Pablo [2 ]
机构
[1] Univ Castilla La Mancha, E-13071 Ciudad Real, Spain
[2] Univ Cantabria, Santander, Spain
关键词
UML/MARTE; SystemC; VHDL; reconfigurability; automatic code generation;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities, such as the reduction of the total area required in a FPGA by means of functioning overlapping, or the modification of the design after its deployment, where a complete configuration is not needed. However, the design of partially reconfigurable systems is still a complex task. This work focuses on facilitating the design process and proposes a new development framework for dynamically configurable systems from high level UML/MARTE models which, starting from dynamically reconfigurable systems high level UML/MARTE models. Simulation and VHDL code are generated from those models, according to the specification requirements of the reconfigurable hardware captured in the specifications. To demonstrate this approach, a edge detection-based use case has been implemented with the developed framework.
引用
收藏
页码:107 / 114
页数:8
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