Location of stuck-at faults and bridging faults based on circuit partitioning

We propose a method of fault diagnosis at the chip level that reduces the number of simulations required to locate defect site(s) by logically partitioning the circuit into subcircuits. Candidate subcircuits that potentially contain the defect site(s) are identified and further partitioned until the defect site is located with the required resolution. Both stuck-at faults and nonfeedback bridging faults are considered as target fault models to represent defects. At the base of the fault location procedure is a procedure to identify subcircuits that potentially contain the fault site. This procedure is matched to the fault model being considered, thus allowing the same partitioning scheme to be applied to various fault models. The procedure presented here is applicable to combinational and fully scanned sequential circuits. Experimental results are presented to demonstrate the effectiveness of circuit partitioning in reducing the number of fault simulations required to locate a fault.