Impact of Resistive Superconducting Fault Current Limiter and Distributed Generation on Fault Location in Distribution Networks

被引:22
|
作者
Guillen, Daniel [1 ]
Salas, Christian [2 ]
Trillaud, Frederic [3 ]
Castro, Luis M. [4 ]
Tiago Queiroz, Andre [5 ]
Goncalves Sotelo, Guilherme [5 ]
机构
[1] Tecnol Monterrey, Escuela Ingn & Ciencias, Monterrey 64849, Nuevo Leon, Mexico
[2] Univ Nacl Autonoma Mexico, Posgrad Ingn Elect, Cdmx 04510, Mexico
[3] Univ Nacl Autonoma Mexico, Inst Ingn, Cdmx 04510, Mexico
[4] Univ Nacl Autonoma Mexico, Dept Energia Elect, Cdmx 04510, Mexico
[5] Fluminense Fed Univ, Elect Engn Dept, BR-24220900 Niteroi, RJ, Brazil
关键词
Distributed Generation; Distribution Network; Fault Location; Resistive Superconducting Fault-Current; Limiter; COORDINATION; ENHANCEMENT; SIMULATION; DIAGNOSIS;
D O I
10.1016/j.epsr.2020.106419
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Resistive Superconducting Fault-Current limiters (r-SFCL) appear as a new attractive technology to address faults in power grids. Based on a new generation of superconductors, referred to as High-Temperature Superconductors (HTS), they could offer economical benefits compared to more conventional technologies. To understand their impact on the electrical networks, two models of r-SFCL, differing by their complexity, were built to conduct short-circuit analysis. Different fault locations in distribution networks were studied in the standard IEEE 13 node and 34-node test feeders. Both models were validated against experimental data and then cross-checked in the IEEE 13-bus distribution system to determine their relative accuracy when used in practical power grids. Subsequently, using the simplest electrical model of r-SFCL, the 34-bus test system incorporating Distributed Generation (DG) was used to analyze short circuits. It was found that the presence of r-SFCL increases the error of the fault location algorithm. However, it was also demonstrated that a single r-SFCL enables the incorporation of several additional DG in a distribution network by reducing the fault current level by at least 45% depending on its design characteristics and the number of added DG. Finally, an improved algorithm is presented. This algorithm takes into account the r-SFCL resistance in order to reduce the fault location error.
引用
收藏
页数:13
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