Transistor- and circuit-design optimization for low-power CMOS

被引：17

作者：

Chang, Mi-Chang ^{[1
]}

Chang, Chih-Sheng ^{[2
]}

Chao, Chih-Ping ^{[3
]}

Goto, Ken-Ichi ^{[4
]}

Ieong, Meikei ^{[4
]}

Lu, Lee-Chung ^{[2
]}

Diaz, Carlos H. ^{[4
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan

[2] Taiwan Semiconduct Mfg Co Ltd, Hsinchu 300, Taiwan

[3] Taiwan Semiconduct Mfg Co Ltd, R&D Team, Mixed Signal & RF Div, Hsinchu 300, Taiwan

[4] Taiwan Semiconduct Mfg Co Ltd, R&D Team, Adv Device Technol Div, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 01期

关键词：

low power; low-power CMOS; power management; technology scaling; transistor-circuit-design co-optimization;

D O I：

10.1109/TED.2007.911348

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active- and leakage-power control. This paper also addresses the derived trends and implications on I/O and analog-transistor scaling.

引用

页码：84 / 95

页数：12

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