Electrical-Thermal Characterization of Through Packaging Vias in Glass Interposer

被引:22
|
作者
Qian, Libo [1 ]
Xia, Yinshui [1 ]
Shi, Ge [2 ]
Wang, Jiang [1 ]
Ye, Yidie [1 ]
Du, Shimin [3 ]
机构
[1] Ningbo Univ, Fac Elect Engn & Comp Sci, Ningbo 315211, Zhejiang, Peoples R China
[2] China Jiliang Univ, Coll Mech & Elect Engn, Hangzhou 310018, Zhejiang, Peoples R China
[3] Ningbo Univ, Fac Sci & Technol, Ningbo 315211, Zhejiang, Peoples R China
基金
中国国家自然科学基金;
关键词
Electrical-thermal characteristics; equivalent circuit model; glass interposer; tapered through glass vias; THROUGH-SILICON VIAS; CARBON-NANOTUBE; PERFORMANCE ANALYSIS; FABRICATION; TSVS;
D O I
10.1109/TNANO.2017.2722686
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-cost thin glass is developed as a promising material to advanced interposers for high density electrical interconnection in 2.5-D and three-dimensional (3-D) integration. In this paper, the electrical-thermal performance of through glass vias is investigated. The distributed transmission lines model for tapered through glass vias (T-TGVs) in signal-ground-signal type differential structure is first established and validated against the 3-D full-wave electromagnetic simulator. The model is applicable to TGVs made of carbon nanotubes(CNTs) by incorporating CNT quantum and kinetic effects. Using the proposed model, the impact of various parameters on the electrical characteristics of the differential T-TGVs is investigated. It is observed that the inductive element of conductor loss plays a significant role on the electrical performance, which makes the CNT-TGV interconnects show unique electrical characterization that totally different from its through silicon vias (TSVs) counterpart. For example, the signal loss of TGV interconnects in different-mode signaling is even lower than that in common-mode and increasing via pitch increases signal loss. Furthermore, the thermal performance of 2.5-D integration with TGVs is investigated with COMSOL multiphysics. It is shown that TGV is a primary path for heat dissipation and increasing TGV distribution density can significantly lower the peak temperature of 2.5-D integration. Because of high thermal conductivity of CNTs, glass interposer with CNT-TGVs can achieve better thermal performance in comparison to its Cu counterpart.
引用
收藏
页码:901 / 908
页数:8
相关论文
共 50 条
  • [41] ELECTRICAL-THERMAL COUPLED CALCULATION OF AN ASYNCHRONOUS MACHINE
    HATZIATHANASSIOU, V
    XYPTERAS, J
    ARCHONTOULAKIS, G
    ARCHIV FUR ELEKTROTECHNIK, 1994, 77 (02): : 117 - 122
  • [42] Miniaturized Thermal Flow Sensors with Through Silicon Vias for Flip-Chip Packaging
    Sosna, C.
    Kropp, M.
    Lang, W.
    Buchner, R.
    2010 IEEE SENSORS, 2010, : 2460 - 2463
  • [43] Electrical-Thermal Co-Simulation for LFBGA
    Sun Haiyan
    Gao Bo
    Sun Ling
    Zhao Jicong
    Peng Yihong
    Fang Jiaen
    Miao Xiaoyong
    Wang Honghui
    2018 19TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2018, : 1269 - 1272
  • [44] High-Frequency Characterization of Through Package Vias Formed by Focused Electrical-Discharge in Thin Glass Interposers
    Tong, Jialing
    Sato, Yoichiro
    Takahashi, Shintaro
    Imajyo, Nobuhiko
    Peterson, Andrew F.
    Sundaram, Venky
    Tummala, Rao
    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2014, : 2271 - 2276
  • [45] OPTIMIZATION OF A NONLINEAR ELECTRICAL-THERMAL MODEL OF THE SKIN
    Molaei, S. Rasoul
    Jafari, Reza
    Jafari, Sajad
    Abdolmohammadi, Hamid Reza
    BIOMEDICAL ENGINEERING-APPLICATIONS BASIS COMMUNICATIONS, 2013, 25 (03):
  • [46] Electrical Characterization of 3D Through-Silicon-Vias
    Liu, F.
    Gu, X.
    Jenkins, K. A.
    Cartier, E. A.
    Liu, Y.
    Song, P.
    Koester, S. J.
    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 1100 - 1105
  • [47] Electrical Modeling and Characterization of Shield Differential Through-Silicon Vias
    Lu, Qijun
    Zhu, Zhangming
    Yang, Yintang
    Ding, Ruixue
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (05) : 1544 - 1552
  • [48] Electrical-Thermal Co-Analysis of Through Silicon Via with Equivalent Circuit Model
    Min, Qiu
    Li, Er-Ping
    Zhuo, Cheng
    Li, Yong-Sheng
    Zhou, Shi-Yun
    Jin, Jian-Ming
    2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
  • [49] Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results
    Henry, D.
    Charbonnier, J.
    Chausse, P.
    Jacquet, F.
    Aventurier, B.
    Brunet-Manquat, C.
    Lapras, V.
    Anciant, R.
    Sillon, X.
    Dunne, B.
    Hotellier, A.
    Michailos, J.
    EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 35 - +
  • [50] Impact of Copper Through-Package Vias on Thermal Performance of Glass Interposers
    Cho, Sangbeom
    Sundaram, Venky
    Tummala, Rao R.
    Joshi, Yogendra K.
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2015, 5 (08): : 1075 - 1084