Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas

被引：4

作者：

Joubert, O ^{[1
]}

Pargon, E ^{[1
]}

Foucher, J ^{[1
]}

Detter, X ^{[1
]}

Cunge, G ^{[1
]}

Vallier, L ^{[1
]}

机构：

[1] CNRS, Lab Technol Microelect, CEA, LETI, F-38054 Grenoble 9, France

来源：

MICROELECTRONIC ENGINEERING | 2003年 / 69卷 / 2-4期

关键词：

plasma etching; gate patterning; CMOS scaling; critical dimension control;

D O I：

10.1016/S0167-9317(03)00321-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition. (C) 2003 Published by Elsevier B.V.

引用

页码：350 / 357

页数：8

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