Efficient multistage decimation filter using pipeline/interleaving architectures for digital if receiver

被引：0
|
作者：
Tecpanecatl-Xihuitl, JL [1 ]
Bayoumi, MA [1 ]
机构：
[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA
来源：
SCS 2003: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents an efficient multistage decimation filter using a specific decomposition multistage and pipeline/interleaving technique to reduce the amount of multiplications. The multistage decimator filter is an important block on digital IF receivers for advanced dedicated mobile data technology called Mobitex and Ardis networks. The results are presented and compared with current results in the literature. The frequency response shows that the requirements are reached and the amount of multiplications is highly reduced. In each case, we get results with an improvement of 55% and 45% just in the multistage decimation filter. Additionally, using PI techniques we just need a single filter to process the components I, and Q in the IF digital receiver.
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收藏
页码：25 / 28
页数：4
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