MTCML: Analysis, design and optimization of an alternative shallow-depth multiple-tail current mode logic

This paper presents an alternative CML with shallow-depth differential logic. In the proposed methodology, the tail current is dissolved into multiple tails with total current of the parent but with shallower depth from supply or ground to the common-mode point. It is applied on all fully-stacked stages. For non-fully stacked, the procedure will be used on the other pair only while the current separation on the previous point is intact. Analytical details, performance optimization, and design procedures are presented. The shallow-depth feature of the proposed design allows lower supply for low-voltage applications and shows reduced delay. The approach, reaches about 50% improvement on supply voltage against conventional and Folded-SCL. The noticeable disadvantage of the proposed approach is its area/fan-in penalty.