Optimized speaker independent speech recognition system for low cost application

被引：0

作者：

Teh, CC ^{[1
]}

Jong, CC ^{[1
]}

Siek, L ^{[1
]}

Loa, KK ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Singapore 639798, Singapore

来源：

PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 2000年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an ASIC design and implementation of 15-isolated-word, speaker independent speech recognition system for low cost application. The input to the IC is a 12-bit sample with a sampling rate of 11.025 kHz. The delay between the end of a word and the response from the IC is approximately 0.24s. The IC is running at 10 MHz system clock and targeted at 0.35 mum CMOS process. The whole chip, which includes the speech recognition system core, RAM and ROM, contains about 61000 gate counts. The core die size is 1.5mm x 3mm. The current design was simulated in VHDL for hardware implementation and the functionality of the IC was identical to the MATLAB simulation. The system achieves a recognition rate of 89% for the 15 isolated words.

引用

页码：1218 / 1221

页数：4

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