Thermo-Fluidic Characterizations of Multi-Port Compact Thermal Model of Ball-Grid-Array Electronic Package

被引:2
|
作者
Bissuel, Valentin [1 ]
Joly, Frederic [2 ]
Monier-Vinard, Eric [1 ]
Neveu, Alain [2 ]
Daniel, Olivier [1 ]
机构
[1] Thales Corp Engn, 19-21 Ave Morane Saulnier, F-78140 Velizy Villacoublay, France
[2] Univ Paris Saclay, Univ Evry, LMEE, F-91020 Evry, France
关键词
BCI-DCTM; ROM; modal approach; BGA; experimental validation; PROPER ORTHOGONAL DECOMPOSITION; REDUCTION;
D O I
10.3390/en13112968
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
The concept of a single-input/multi-output thermal network was proposed by the Development of Libraries of Physical models for an Integrated design environment (DELPHI) consortium more than twenty years ago. The present work highlights the recent improvements made to efficiently derive a low-computing-effort model from a fully detailed numerical model and to characterize its performances. The temperature predictions of a deduced ball-grid-array (BGA) dynamic compact thermal model are compared to those of a realistic three-dimensional representation, including the large set of internal copper traces, as well as its board structure, which has been validated by experiment. The current study discloses a method for creating an amalgam reduced-order modal model (AROMM) for that electronic component family that allows the preservation of the geometry integrity and shortening scenarios computation. Typically, the AROMM method reduces by a factor of 600 the computation time needed to obtain the solution while keeping the error on the maximum temperature below 2%. Then, a meta-heuristic optimization is run to derive a more practical low-order resistor capacitor model that enables a thermo-fluidic analysis at the board level. Based on the calibrated numerical model, a novel AROMM method was investigated in order to address the chip behavior submitted to multiple heat sources. The first results highlight the capability to enforce a non-uniform power distribution on the upper surface of the silicon chip. Thus, the chip design layout can be analyzed and optimized to prevent thermal and reliability issues.
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页数:17
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