A study of control independence in superscalar processors

Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However irs performance potential under practical hardware constraints is not known, and even less is understood about the factors that contribute to or limit the performance of control independence. Important aspects of control independence are identified and singled out for study, and a series of idealized machine models are used to isolate and evaluate these aspects. It is shown that much of the performance potential of control independence is lost due to data dependences and wasted resources consumed by incorrect control dependent instructions. Even so, control independence can close the performance gap between real and perfect branch prediction by as much as half Next, important implementation issues are discussed and some design alternatives are given. This is followed by a more derailed set of simulations, where the key implementation features are realistically modeled. These simulations show typical performance improvements of 10-30%.