Fabrication and Electrical Characterization of Parylene-HT Liner Bottom-up Copper Filled Through Silicon Via (TSV)

被引：0

作者：

Tung, Bui Thanh ^{[1
]}

Cheng, Xiaojin ^{[1
,2
]}

Watanabe, Naoya ^{[1
]}

Kato, Fumiki ^{[1
]}

Kikuchi, Katsuya ^{[1
]}

Aoyagi, Masahiro ^{[1
]}

机构：

[1] Natl Inst Adv Ind Sci & Technol, Nanoelect Res Inst NeRI, Tsukuba, Ibaraki, Japan

[2] Univ Loughborough, Loughborough, Leics, England

来源：

2014 IEEE CPMT SYMPOSIUM JAPAN (ICSJ) | 2014年

关键词：

Parylene-HT; TSV liner; electroplating; bottom-up copper filled; TSV; DEPOSITION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this study, Parylene-HT, the newest commercially available parylene with the lowest dielectric constant and highest temperature tolerance within all the series, was investigated as insulation/liner in the application of through-silicon-via (TSV). Bottom-up copper filled TSV with 1 mu m Parylene-HT insulator was realized on a 100 mu m-thick Si wafer through via etching, parylene vapor deposition, and electroplating processes. The fabrication process on the 36 mu m diameter TSVs, are reported here, as well as their electrical properties, including DC leakage and capacitance.

引用

页码：154 / 157

页数：4

共 44 条

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