PACT XPP architecture in adaptive system-on-chip integration

The paper gives first the actual status and results of a dynamically Configurable System-on-Chip (CSoC) integration, consisting of a SPARC-compatible LEON processor-core, a coarse-grain XPP-array of suitable size from PACT XPP Technologies AG (Muenchen, Germany), and efficient multi-layer Amba-based communication interfaces. Within this industrial/academic research project experimental standard cell synthesis and post-layout analysis were done onto 0.18 and 0.13 mum UMC CMOS technologies at Universitaet Karlsruhe (TH). The paper will in addition describe PACT's newest XPP architectures realizing a new runtime reconfigurable data processing technology that replaces the concept of instruction sequencing by configuration sequencing with high performance application areas envisioned from embedded signal processing to co-processing in different DSP-like and mobile application environments. The underlying programming model is motivated by the fact, that future oriented applications need to process streams of data decomposed into smaller sequences which are processed in parallel. Latest commercial chip synthesis were performed successfully onto 0.13 mum STMicro CMOS technology.