On the impact of structural circuit partitioning on SAT-based combinational circuit verification

被引：0
|
作者：
Herbstritt, M [1 ]
Kmieciak, T [1 ]
Becker, B [1 ]
机构：
[1] Univ Freiburg, Inst Comp Sci, D-79110 Freiburg, Germany
来源：
5TH INTERNATIONAL WORKSHOP ON MICROPROCESSOR TEST AND VERIFICATION: COMMON CHALLENGES AND SOLUTIONS, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this work we present an approach for SAT-based combinational circuit verification using partitionings of the set of primary outputs. We formally analyze the applied partitioning heuristics for the first time and present a closed verification framework incorporating traditional techniques. We report on experiments using our partitioning-based verification procedure that result in speedups of 276% on the average compared to traditional techniques.
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页码：50 / 55
页数：6
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