Fully parallel fractional motion estimation for H.264/AVC encoder

被引：0

作者：

Ta, Nam Thang ^{[1
]}

Kim, Jae Hoon ^{[1
]}

Choi, Jun Rim ^{[1
]}

Kim, Shi Hye ^{[1
]}

Hwang, Seon Cheol ^{[2
]}

机构：

[1] Kyungpook Natl Univ, Sch Elect Engn & Comp Sci, Taegu, South Korea

[2] Induk Univ, Seoul, South Korea

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND INTELLIGENT SYSTEMS, PROCEEDINGS, VOL 4 | 2009年

关键词：

integer; fractional; motion estimation; half-quarter pel; H.264/AVC; ARCHITECTURE; DESIGN;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Fractional motion estimation always takes much processing time because of variety of motion vectors and two-step sequential half-quarter pel. In this paper, we propose the architecture of fractional engine in fully parallel manner. Instead of sequential processing two-step of half-quarter refinement, integer-half-quarter pel is processed in parallel manner in order to double the speed as well as the throughput. Using Chartard 0.18 mu m CMOS 1P5M technology, the proposed architecture is implemented with 412k logic gates and achieves the throughput of 255 kMBs/s supporting HDTV1080p 30 fps when operating at the frequency of 220MHz.

引用

页码：306 / +

页数：2

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