A continuous-time reduced-sample-rate ΔΣ-pipeline ADC for broadband wireless applications

被引：0
|
作者：
Ge, Fuding [1 ]
Jalali-Farahani, Bahar [1 ]
Song, Hongjiang [1 ]
Ismail, Mohammed [2 ]
机构：
[1] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85287 USA
[2] Ohio State Univ, Dept Elect & Comp Engn, Columbus, OH 43210 USA
来源：
2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 | 2007年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a continuous-time 2-0 cascade delta-sigma modulator. The first stage of the modulator is a second-order continuous-time modulator with low-distortion structure. The second stage is a pipeline ADC with reduced sample rate. Matlab simulation shows it can achieve ma3imum SQNR of 77 dB with OSR--8 for the first stage and OSR=2 for the second stage. Circuit level implementation of the modulator is given and the effects of circuit nonideal properties, such as RC time-constant variation, finite opamp gain and bandwidth, on the modulator performance are discussed.
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页码：772 / +
页数：2
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