共 50 条
- [41] Design of Low Power 5-bit Hybrid Flash ADC [J]. 2016 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2016, : 343 - 348
- [42] A 45nm CMOS 0.35V-Optimized Standard Cell Library for Ultra-Low Power Applications [J]. ISLPED 09, 2009, : 225 - 230
- [43] Design of Low-power Arithmetic Logic Circuits for 45 nm CMOS Technology [J]. 2022 IEEE 21ST MEDITERRANEAN ELECTROTECHNICAL CONFERENCE (IEEE MELECON 2022), 2022, : 7 - 12
- [44] A Novel Low Leakage and High Density 5T CMOS SRAM Cell in 45nm Technology [J]. 2014 RECENT ADVANCES IN ENGINEERING AND COMPUTATIONAL SCIENCES (RAECS), 2014,
- [45] Performance analysis of novel domino XNOR gate in sub 45nm CMOS technology [J]. 1600, World Scientific and Engineering Academy and Society, Ag. Ioannou Theologou 17-23, Zographou, Athens, 15773, Greece (12):
- [46] A 4GHz-Bandwidth Op-Amp-Free Track-and-Hold and 6-bit Flash ADC in 45nm SOI CMOS [J]. 2013 IEEE 13TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF), 2013, : 126 - 128
- [47] A 10 GS/s, 3-Bit ADC with Novel Decoder in SiGe BiCMOS Technology [J]. 2018 3RD IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM), 2018, : 196 - 200
- [48] A 2.4 GHz CMOS Ultra Low Power Low Noise Amplifler Design with 65 nm CMOS Technology [J]. 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1480 - 1483
- [49] A Novel Power Gating Technique for 3-Bit Flash Analog to Digital Converter [J]. 2ND INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) 2015, 2015, : 897 - 901
- [50] A 4 bit Low Power Process Tolerant Flash ADC in 0.18μm CMOS [J]. 2015 3RD INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, COMMUNICATION AND NETWORKING (ICSCN), 2015,