An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network

被引:3
|
作者
Liu, Baicheng [1 ]
Chen, Song [1 ]
Kang, Yi [1 ]
Wu, Feng [1 ]
机构
[1] Univ Sci & Technol China, Sch Microelect, Hefei 230027, Peoples R China
基金
中国国家自然科学基金;
关键词
D O I
10.1109/asicon47005.2019.8983637
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Memory and computation cost limit the applications of Convolutional Neural Networks (CNN) on mobile devices. Binary CNN (BCNN) is a quantized neural network, which can reduce memory requirement and achieve multiplication-free computation. This paper focuses on BCNN. First, we proposed a hardware friendly CNN model to decrease the inference accuracy loss by eliminating the decimal part of each floating number. Second, we presented a fully pipelined on-chip BCNN architecture. The architecture has systolic data flow and an inter-layer pipeline, which ensures weights reuse and high throughputs. The results show that we achieve an inference accuracy of 99.04% for the MNIST dataset on the Pytorch platform and 98.91% in the hardware architecture, which means the inference accuracy loss is only 0.13%; the inference accuracy loss without this model is 0.41%. Besides, this architecture can achieve 23.08k: qfps and 353.5 GOP/s/W at 120MHz with small resource use while processing the BCNN.
引用
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页数:4
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