An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network

被引:3
|
作者
Liu, Baicheng [1 ]
Chen, Song [1 ]
Kang, Yi [1 ]
Wu, Feng [1 ]
机构
[1] Univ Sci & Technol China, Sch Microelect, Hefei 230027, Peoples R China
基金
中国国家自然科学基金;
关键词
D O I
10.1109/asicon47005.2019.8983637
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Memory and computation cost limit the applications of Convolutional Neural Networks (CNN) on mobile devices. Binary CNN (BCNN) is a quantized neural network, which can reduce memory requirement and achieve multiplication-free computation. This paper focuses on BCNN. First, we proposed a hardware friendly CNN model to decrease the inference accuracy loss by eliminating the decimal part of each floating number. Second, we presented a fully pipelined on-chip BCNN architecture. The architecture has systolic data flow and an inter-layer pipeline, which ensures weights reuse and high throughputs. The results show that we achieve an inference accuracy of 99.04% for the MNIST dataset on the Pytorch platform and 98.91% in the hardware architecture, which means the inference accuracy loss is only 0.13%; the inference accuracy loss without this model is 0.41%. Besides, this architecture can achieve 23.08k: qfps and 353.5 GOP/s/W at 120MHz with small resource use while processing the BCNN.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] An Energy-Efficient Convolutional Neural Network Processor Architecture Based on a Systolic Array
    Zhang, Chen
    Wang, Xin'an
    Yong, Shanshan
    Zhang, Yining
    Li, Qiuping
    Wang, Chenyang
    [J]. APPLIED SCIENCES-BASEL, 2022, 12 (24):
  • [2] An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
    Wang, Yizhi
    Lin, Jun
    Wang, Zhongfeng
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (02) : 280 - 293
  • [3] COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks based on Systolic Array
    Yin, Chen
    Chen, Qiang
    Tian, Miren
    Ji, Mohan
    Zou, Chenglong
    Wang, Yin'an
    Wang, Bo
    [J]. 2017 IEEE 23RD INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2017, : 180 - 189
  • [4] PERMCNN: Energy-Efficient Convolutional Neural Network Hardware Architecture With Permuted Diagonal Structure
    Deng, Chunhua
    Liao, Siyu
    Yuan, Bo
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2021, 70 (02) : 163 - 173
  • [5] Energy-Efficient Architecture for FPGA-based Deep Convolutional Neural Networks with Binary Weights
    Duan, Yunzhi
    Li, Shuai
    Zhang, Ruipeng
    Wang, Qi
    Chen, Jienan
    Sobelman, Gerald E.
    [J]. 2018 IEEE 23RD INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP), 2018,
  • [6] An Approach of Binary Neural Network Energy-Efficient Implementation
    Gao, Jiabao
    Liu, Qingliang
    Lai, Jinmei
    [J]. ELECTRONICS, 2021, 10 (15)
  • [7] Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic
    Suzuki, Daisuke
    Oka, Takahiro
    Tamakoshi, Akira
    Takako, Yasuhiro
    Hanyu, Takahiro
    [J]. IEICE NONLINEAR THEORY AND ITS APPLICATIONS, 2021, 12 (04): : 695 - 710
  • [8] Energy-Efficient Design of Processing Element for Convolutional Neural Network
    Choi, Yeongjae
    Bae, Dongmyung
    Sim, Jaehyeong
    Choi, Seungkyu
    Kim, Minhye
    Kim, Lee-Sup
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64 (11) : 1332 - 1336
  • [9] An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network
    Chakraborty, Subhradip
    Kushwaha, Dinesh
    Goel, Abhishek
    Singla, Anmol
    Bulusu, Anand
    Dasgupta, Sudeb
    [J]. 2024 25TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2024, 2024,
  • [10] Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
    Chen, Yu-Hsin
    Emer, Joel
    Sze, Vivienne
    [J]. 2016 ACM/IEEE 43RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), 2016, : 367 - 379