An FPGA-based Prototyping Framework for Networks-on-Chip

This paper presents a modular prototyping framework for fast test and evaluation of Networks-on-Chip (NoCs). It targets RTL implementations of NoCs and similar communications infrastructures. Our combined hardware-software approach diminishes the main drawbacks of both domains: The slow speed of RTL simulation and the inflexibility of hardware prototypes. While the NoC under test is instantiated on an FPGA, traffic generation is realized at runtime in software. The framework features flexible and simple software interfaces as found in RTL simulation or abstract modeling toolkits and achieves higher speeds than RTL simulations. Real-world traffic benchmarks in form of dependency-driven stimuli (Netrace), as well as generation of synthetic traffic and transmission of arbitrary packets is supported. In order to adapt to varying software processing times for traffic generation the NoC under test is supplied with clock pulses by special clocking resources under software control. This avoids using a fixed slow clock speed for the NoC which accounts for the worst case software timing. In our case study we achieved average effective NoC clock speeds of 16 kHz to 39 kHz using synthetic network traffic and Netrace trace files, while RTL simulations ran at about 12 Hz. This corresponds to a speedup of over 1000.