Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration

被引:0
|
作者
Jiang, Zhewei [2 ]
Yin, Shihui [1 ]
Kim, Minkyu [1 ]
Gupta, Tushar [3 ]
Seok, Mingoo [2 ]
Seo, Jae-sun [1 ]
机构
[1] Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85281 USA
[2] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA
[3] Synopsys, Mountain View, CA USA
关键词
In-memory computing; SRAM; deep learning accelerator; deep neural networks; double-buffering;
D O I
10.1109/ieeeconf44664.2019.9048678
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We present Vesti, a Deep Neural Network (DNN) accelerator optimized for energy-constrained hardware platforms such as mobile, wearable, and Internet of Things (IoT) devices. Vesti integrates instances of in-memory computing (IMC) SRAM macros with an ensemble of peripheral digital circuits for dataflow management. The IMC SRAM macros eliminate the data access bottleneck that hinders conventional ASIC implementations performing dot-product computation, while the peripheral circuits improve the macros' parallelism and utilization for practical applications. Vesti supports large-scale DNNs with configurable activation precision, substantially improving chip-level energy-efficiency with favorable accuracy trade-off. The Vesti accelerator is designed and laid out in 65 nm CMOS, demonstrating ultra-low energy consumption of less than <20nJ for MNIST classification and <40 mu J for CIFAR-10 classification at 1.0V supply.
引用
收藏
页码:1516 / 1521
页数:6
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