On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

被引：4
|
作者：
Chang, CY [1 ]
Ker, MD [1 ]
机构：
[1] Ind Technol Res Inst, Syst On Chip Technol Ctr, Analog IP Sect, Hsinchu, Taiwan
来源：
2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2001年
关键词：
D O I：
10.1109/VTSA.2001.934529
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
ESD protection in RF integrated circuits has several considerations: low parasitic capacitance, constant input capacitance, and insensitive to substrate coupling noise. In this paper, a new ESD protection design with polysilicon diodes for RF IC applications is proposed and characterized. The proposed polysilicon diode is constructed by polysilicon layer in a general CMOS process with a central un-doped region. The polysilicon diode with variation on the width of the central un-doped region is characterized at different temperatures. An on-chip ESD protection circuit realized with the stacked polysilicon diodes to reduce the total input capacitance for GHz RF application is demonstrated.
引用
收藏
页码：240 / 243
页数：4
相关论文
共 37 条
  • [21] Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
    Ker, MD
    Hsu, KC
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (02) : 235 - 249
  • [22] On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation
    Ker, Ming-Dou
    Yen, Cheng-Cheng
    Shih, Pi-Chia
    IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2008, 50 (01) : 13 - 21
  • [23] Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process
    Ker, MD
    Chen, TY
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (04) : 1050 - 1057
  • [24] On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
    Ker, MD
    Lin, KH
    Chuang, CH
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (10) : 1628 - 1635
  • [25] Design of Polysilicon-Gate DDSCR Device For RF Chip's ESD Protection Based on 0.18μm BCD Process
    Jin, Xiangliang
    Wang, Yang
    2019 CROSS STRAIT QUAD-REGIONAL RADIO SCIENCE AND WIRELESS TECHNOLOGY CONFERENCE (CSQRWC), 2019,
  • [26] Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology
    Shiu, Yu-Da
    Chuang, Che-Hao
    Ker, Ming-Dou
    2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 56 - +
  • [27] ESD Self-Protection Design on 2.4-GHz T/R Switch for RF Application in CMOS Process
    Lin, Chun-Yu
    Liu, Rui-Hong
    Ker, Ming-Dou
    2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
  • [28] Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process
    Ker, MD
    Hsu, KC
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (02) : 397 - 405
  • [29] MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process
    Ker, MD
    Lin, KH
    Chuang, CH
    2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2003, : 84 - 87
  • [30] Design and modeling of compact on-chip transformer/balun using multi-level metal windings for RF integrated circuits
    Liang, T
    Gillis, J
    Wang, D
    Cooper, P
    2001 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2001, : 117 - 120
1234