On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

被引：4

作者：

Chang, CY ^{[1
]}

Ker, MD ^{[1
]}

机构：

[1] Ind Technol Res Inst, Syst On Chip Technol Ctr, Analog IP Sect, Hsinchu, Taiwan

来源：

2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VTSA.2001.934529

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

ESD protection in RF integrated circuits has several considerations: low parasitic capacitance, constant input capacitance, and insensitive to substrate coupling noise. In this paper, a new ESD protection design with polysilicon diodes for RF IC applications is proposed and characterized. The proposed polysilicon diode is constructed by polysilicon layer in a general CMOS process with a central un-doped region. The polysilicon diode with variation on the width of the central un-doped region is characterized at different temperatures. An on-chip ESD protection circuit realized with the stacked polysilicon diodes to reduce the total input capacitance for GHz RF application is demonstrated.

引用

页码：240 / 243

页数：4

共 37 条

[1] On-chip ESD protection design by using polysilicon diodes in CMOS process
Ker, MD
Chen, TY
Wang, TH
Wu, CY
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (04) : 676 - 686
[2] ESD protection design for CMOS RF integrated circuits using polysilicon diodes
Ker, MD
Chang, CY
MICROELECTRONICS RELIABILITY, 2002, 42 (06) : 863 - 872
[3] On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process
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[4] Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
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[5] Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process
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[6] SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
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[7] On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application
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[8] ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process
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[9] On-Chip ESD Protection Design for HV Integrated Circuits
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[10] ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design
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