共 50 条
- [21] A 23mW 24GS/s 6b Time-Interleaved Hybrid Two-Step ADC in 28nm CMOS 2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS), 2016,
- [22] A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
- [23] A 10b 20-Msample/s 28mW CMOS ADC in ASIC process ELEVENTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE - PROCEEDINGS, 1998, : 57 - 61
- [24] A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW Single-Channel SAR ADC in 28nm Bulk CMOS ESSCIRC 2017 - 43RD IEEE EUROPEAN SOLID STATE CIRCUITS CONFERENCE, 2017, : 167 - 170
- [27] A 12-bit 60-MS/s 36-mW SHA-less opamp-sharing pipeline ADC in 130 nm CMOS JOURNAL OF INSTRUMENTATION, 2016, 11
- [28] A 0.35mW 12b 100MS/s SAR-Assisted Digital Slope ADC in 28nm CMOS 2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2016, 59 : 462 - U650
- [30] A 10b 160-MS/s Domino-SAR ADC in 90nm CMOS 2018 7TH IEEE INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE), 2018, : 76 - 77