An issue logic for Superscalar Microprocessors

被引：0

作者：

Shiao, FJ ^{[1
]}

Shieh, JJ ^{[1
]}

机构：

[1] Tatung Univ, Dept Comp Sci & Engn, Taipei, Taiwan

来源：

COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING | 2003年

关键词：

issue logic; issue table; superscalar;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectively due to two reasons. One reason is the complexity design will reduce the clock frequency seriously and another reason is data dependency makes the instructions parallelism unable to break through the dataflow limitation. In this paper, we propose speculative wakeup logic to enhance the instructions parallelism. In order to issue more instructions every cycle, an issue table is added to help the select logic select the suitable instructions to issue. Simulation results show the average IPC is increased by 22.5% in SPECInt and 45% in SPECfp over a conventional architecture.

引用

页码：268 / 271

页数：4

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