The Median Filtering Algorithm's Fast Implementation in FPGA

被引：1

作者：

Zhang Daode ^{[1
]}

Pan Yurong ^{[1
]}

Hu Xinyu ^{[1
]}

Yang Guangyou ^{[1
]}

Xu Cheng ^{[1
]}

机构：

[1] Hubei Univ Technol, Hubei Prov Key Lab Modern Manufature Qual Engn, Sch Mech Engn, Wuhan 430068, Peoples R China

来源：

FRONTIERS OF MANUFACTURING SCIENCE AND MEASURING TECHNOLOGY, PTS 1-3 | 2011年 / 230-232卷

关键词：

FPGA; Image Processing; Median Filtering; Threshold;

D O I：

10.4028/www.scientific.net/AMR.230-232.1054

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Based on FPGA'S Balance and exchange principle of area and speed, Using the FPGA internal rich logic resources and powerful hardware characteristics, the traditional median filtering algorithm is reduced to 2 clock cycle, Greatly improving the image processing speed. And by using threshold, in a certain extent, reducing the image fuzzy phenomena brought by the median filter. The results of test show that the system runs stability, the time of achieving the median filtering algorithm are narrowed to the shortest clock cycle.

引用

页码：1054 / +

页数：2

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