Implementation of Public Key Crypto Processor with Probabilistic Encryption on FPGA for Nodes in Wireless Sensor Networks

Cryptographic algorithms are fundamental to the secure communications over Wireless Sensor Networks. This paper presents complete public key cryptosystem with mathematical model essential for designing a cryptographic algorithm that integrates probabilistic encryption. The encryption process is presented as a secured pseudo random number generator that supports key generation process. The main goal of our work is to design Public Key Crypto Processor with modification of Public Key Algorithms, RSA and ECC for Wireless Sensor Node architecture considering speed, time and area as the design parameters. The Crypto Processor is simulated on different FPGA devices, with key length 64 bits. The comparison of the performance is done with respect to area and speed. The proposed Public key Crypto algorithm is modeled using Verilog and synthesized on Spartan 3 and 6, Virtex 7, Kintex 7 and Artix7. Combinational path delay is not determined in any of the module implemented. The design satisfies the requirements of resource constrained Wireless Sensor Network's devices with 0.05% i.e., less device utilization with speed of 968.9MHz.