A Digital ISFET Sensor with In-Pixel ADC

被引:24
|
作者
Han, Jinzhao [1 ]
Cacho-Soblechero, Miguel
Douthwaite, Matthew
Georgiou, Pantelis
机构
[1] Imperial Coll London, Dept Elect & Elect Engn, London, England
来源
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年
关键词
ISFET; DNA amplification; Digital Pixel Sensor (DPS); Lab-on-a-chip; In-Pixel ADC; CMOS; ARRAY; VISION;
D O I
10.1109/ISCAS51556.2021.9401244
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a novel ISFET architecture with in-pixel ADC for large-scale integration and on-chip computational capabilities. Each pixel is composed by a comparator connected to a set of memory elements, storing in-pixel each conversion. Using this sensing scheme, the entire frame of ISFET pixels is acquired and stored in one single ADC cycle, eliminating the need for global or column-level ADCs and making this architecture scalable to larger arrays without instrumentation overhead. To enable compensation of ISFET non-idealities such as trapped charge, a novel gate-bootstrapping mechanism is introduced, enhancing the ADC dynamic range without additional circuitry and accommodating a trapped charge compensation range of 4.45 V. Fabricated in standard 180nm CMOS technology, the system is composed by a 16x16 ISFET array, a global DAC and a Digital Control Unit that enables operation and off-chip communication. The entire frame is acquired in 51.2 mu s with a pixel power consumption of 10.15 mu W, while storing the result in-pixel and eliminating the need for off-chip memories.
引用
收藏
页数:5
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