A Digital ISFET Sensor with In-Pixel ADC

This paper presents a novel ISFET architecture with in-pixel ADC for large-scale integration and on-chip computational capabilities. Each pixel is composed by a comparator connected to a set of memory elements, storing in-pixel each conversion. Using this sensing scheme, the entire frame of ISFET pixels is acquired and stored in one single ADC cycle, eliminating the need for global or column-level ADCs and making this architecture scalable to larger arrays without instrumentation overhead. To enable compensation of ISFET non-idealities such as trapped charge, a novel gate-bootstrapping mechanism is introduced, enhancing the ADC dynamic range without additional circuitry and accommodating a trapped charge compensation range of 4.45 V. Fabricated in standard 180nm CMOS technology, the system is composed by a 16x16 ISFET array, a global DAC and a Digital Control Unit that enables operation and off-chip communication. The entire frame is acquired in 51.2 mu s with a pixel power consumption of 10.15 mu W, while storing the result in-pixel and eliminating the need for off-chip memories.