A reconfigurable architecture for scanning biosequence databases

被引:1
|
作者
Oliver, T [1 ]
Schmidt, B [1 ]
Maskell, DL [1 ]
Vinod, AP [1 ]
机构
[1] Nanyang Technol Univ, Sch Comp Sci, Singapore 639798, Singapore
关键词
D O I
10.1109/ISCAS.2005.1465706
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithms exist for this problem, the required scanning time is still very high. The scan time requirements are likely to become even more severe because of the rapid growth in size of these databases. Thus, finding fast solutions is of high importance to research in this area. In this paper we present a new approach to biosequence database scanning using reconfigurable FPGA-based hardware platforms to gain high performance at low cost. To derive an efficient mapping onto this type of architecture, we have designed fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query. This results in an implementation with significant runtime savings on a standard FPGA.
引用
收藏
页码:4799 / 4802
页数:4
相关论文
共 50 条
  • [41] SURVEY ON RECONFIGURABLE FIR FILTER ARCHITECTURE
    Dinesh, P. S.
    Manikandan, M.
    [J]. 2017 FOURTH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, COMMUNICATION AND NETWORKING (ICSCN), 2017,
  • [42] A reconfigurable cache architecture embedded systems
    Modarressi, Mehdi
    Hessabi, Shaahin
    Goudarzi, Maziar
    [J]. 2006 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-5, 2006, : 2247 - +
  • [43] A General Reconfigurable Architecture for the BLAST Algorithm
    Euripides Sotiriades
    Apostolos Dollas
    [J]. The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2007, 48 : 189 - 208
  • [44] Reconfigurable software for open architecture controllers
    Wang, SG
    Shin, KG
    [J]. 2001 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION, VOLS I-IV, PROCEEDINGS, 2001, : 4090 - 4095
  • [45] A Dynamically Reconfigurable Architecture for Smart Grids
    Villa, David
    Martin, Cleto
    Jesus Villanueva, Felix
    Moya, Francisco
    Carlos Lopez, Juan
    [J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2011, 57 (02) : 411 - 419
  • [46] A compilation framework for a dynamically reconfigurable architecture
    David, R
    Chillet, D
    Pillement, S
    Sentieys, O
    [J]. FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS: RECONFIGURABLE COMPUTING IS GOING MAINSTREAM, 2002, 2438 : 1058 - 1067
  • [47] An efficient reconfigurable image compression architecture
    Perumal, D. Ulagalandha
    Kumar, S. Arun
    Prasanth, S.
    Kumar, P. Vasantha
    Kannan, M.
    Vaidehi, V.
    [J]. 2007 INTERNATIONAL CONFERENCE OF SIGNAL PROCESSING, COMMUNICATIONS AND NETWORKING, VOLS 1 AND 2, 2006, : 265 - +
  • [48] A reconfigurable multifunction computing cache architecture
    Kim, H
    Somani, AK
    Tyagi, A
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9 (04) : 509 - 523
  • [49] Mapping Method for Dynamically Reconfigurable Architecture
    Kuroda, Akira
    Koezuka, Mayuko
    Matsuzaki, Hidenori
    Yoshikawa, Takashi
    Asano, Shigehiro
    [J]. PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, : 757 - 762
  • [50] Design of Reconfigurable Samba Bus Architecture
    Chitra, S. Hema
    Vanathi, P. T.
    Kumar, K. Naresh
    [J]. PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON CONTROL AUTOMATION, COMMUNICATION AND ENERGY CONSERVATION INCACEC 2009 VOLUME II, 2009, : 602 - 607