A ΣΔ fractional-N synthesizer for GSM standard specifications

被引：0
|
作者：
Mnif, H. [1 ]
Fakhfakh, M. [1 ]
Krout, I. [1 ]
Barhoumi, M. [1 ]
Loulou, M. [1 ]
机构：
[1] Natl Engn Sch Sfax, LETI, Sfax, Tunisia
来源：
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年
关键词：
frequency synthesizer; characterization; optimization; algorithm; phase-locked loop (PLL); fractional-N; GSM;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We describe in this paper a new method for the characterization and optimization with heuristic algorithm of fractional-N synthesizer. This method will be applied to GSM application. The treated synthesizer based in the use a type-H third order Sigma Delta modulator generates signals in 935-960 MHz range with 200 KHz resolution with a spur of less than -80 dBc/Hz. Optimal parameters values are so determined and verified by different simulations.
引用
收藏
页码：1121 / 1124
页数：4
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