Parallel architecture for high-speed Reed-Solomon codec

This paper presents a parallel architecture for a high-speed Reed-Solomon (RS) encoder and decoder (codec) LSI. Since the architecture allows H symbols to be processed in parallel the codec LSI achieves a data rate of mLH b/s where m is the symbol size (m bits per symbol), L is the clock frequency of the circuit, and H is an arbitrary integer. As an example, we investigate hardware complexity, delay and critical path length for a (2.55-251) RS code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with H the proposed architecture is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that parallel RS codecs, which can keep up with optical transmission rates, i.e., several giga bits/sec. could be implemented on one LSI chip using current CMOS technology.