Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

被引:20
|
作者
Rashidi, Bahram [1 ]
机构
[1] Ayatollah Boroujerdi Univ, Dept Elect Engn, Boroujerd 6919969411, Iran
关键词
logic circuits; Internet of Things; cryptography; CMOS digital integrated circuits; variable key size; SIMON; LED ciphers; key sizes; adaptive security level; PRESENT ciphers; flexible architectures; flexible structures; lightweight block ciphers; Internet of Things systems; data-sensitive applications; IoT systems; execution time; computational resources; encryption algorithms; IoT communication; high-throughput hardware structures; IoT applications; CMOS technology; area-optimised logic circuits; size; 180; 0; nm; word length 64 bit to 256 bit; HARDWARE ARCHITECTURES; CRYPTANALYSIS; SECURITY; INTERNET; DEVICES; THINGS;
D O I
10.1049/iet-cds.2019.0363
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Security and privacy of the Internet of Things (IoT) systems are critical challenges in many data-sensitive applications. The IoT systems are constrained in terms of execution time, flexibility and computational resources. In recent years, many encryption algorithms have been proposed to provide the security of IoT communication. In this study, flexible and high-throughput hardware structures of the PRESENT, SIMON, and LED lightweight block ciphers are presented for IoT applications. The proposed flexible structures can perform various configurations of these block ciphers to support variable key sizes. For example, the PRESENT, SIMON, and LED ciphers support key sizes (80, 128 bits), (96, 144, 128, 192, and 256 bits), and (64, 128 bits), respectively. Therefore, these architectures provide versatile implementations that enable adaptive security level using a variable key size. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. In the PRESENT and LED ciphers, the S-boxes are implemented based on area-optimised logic circuits. The implementation results of proposed flexible architectures are achieved in 180 nm CMOS technology. Area, throughput and throughput/area of the proposed structures have improved compared to other related works.
引用
收藏
页码:369 / 380
页数:12
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