Digital Enhancement of Frequency Synthesizers

被引:0
|
作者
Ouda, Mahmoud [1 ]
Hegazi, Emad [1 ]
Ragai, Hany F. [1 ]
机构
[1] Ain Shams Univ, Dept Elect & Commun, Cairo, Egypt
关键词
All digital PLL (AD-PLL); sigma delta frequency discriminator (Sigma Delta FD); Jitter; phase domain; phase noise; PLL; voltage-controlled oscillator (VCO);
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
in this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital Sigma Delta-frequency discriminator. Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits and can report digital numbers corresponding to the close in phase noise level of the PLL to a digital BIST controller. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes.
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页码:973 / 976
页数:4
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