Digital Enhancement of Frequency Synthesizers

in this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital Sigma Delta-frequency discriminator. Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits and can report digital numbers corresponding to the close in phase noise level of the PLL to a digital BIST controller. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes.