VHDLStyler -: A script-based tool for IP design modification

被引：0
|
作者：
Büchner, T [1 ]
Smith, C [1 ]
机构：
[1] IBM Deutsch Entwicklung GmbH, Boblingen, Germany
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a method to enable the transition from a given design environment to a modern SoC design flow at minimal cost, and with increased productivity for future designs. A Java-based tool is presented that allows the script-based modification of existing VHDL code for a wide range of applications.
引用
收藏
页码：297 / 298
页数：2
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