Chaotic Dynamics and FPGA Implementation of a Fractional-Order Chaotic System With Time Delay

This article proposes a numerical solution approach and Field Programmable Gate Array implementation of a delayed fractional-order system. The proposed method is amenable to a sufficiently efficient hardware realization. The system's numerical solution and hardware realization have two requirements. First, the delay terms are implemented by employing LookUp Tables to keep the already required delayed samples in the dynamical equations. Second, the fractional derivative is numerically approximated using Grunwald-Letnikov approximation with a memory window size, L, according to the short memory principle such that it balances between accuracy and efficiency. Bifurcation diagrams and spectral entropy validate the chaotic behaviour of the system for commensurate and incommensurate orders. Additionally, the dynamic behaviour of the system is studied versus the delay parameter, tau, and the window size, L. The system is realized on Nexys 4 Artix-7 FPGA XC7A100T with throughput 1.2 Gbit/s and hardware resources utilization 15% from the total LookUp Tables and 4% from the slice registers. Oscilloscope experimental results verify the numerical solution of the delayed fractional-order system. The amenability to digital hardware realization, which is experimentally validated in this article, is added to the system's advantages and encourages its utilization in future digital applications such as chaos control and synchronization and chaos-based communication applications.