High performance FPGA implementation of Data Encryption Standard

被引：0
|
作者：
Abdelwahab, Murtada. M. [1 ]
机构：
[1] Univ Gezira, Fac Engn & Technol, Dept Elect Engn, Wad Madani, Sudan
来源：
2015 INTERNATIONAL CONFERENCE ON COMPUTING, CONTROL, NETWORKING, ELECTRONICS AND EMBEDDED SYSTEMS ENGINEERING (ICCNEEE) | 2015年
关键词：
Encryption; Decryption; FPGA; DES; symmetric;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The proposed cryptographic system represents a compact data encryption algorithm (DEA). The implementation provides a short path of encryption and consists of single round. It used only 303 slice and achieved throughput of 278.282 Mbps. The results are shown in the form of chip area performance and performance/slice. The results are compared graphically with similar encryption implementations and founded very competitive.
引用
收藏
页码：37 / 40
页数：4
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