Unbiased Finite-Memory Digital Phase-Locked Loop

被引:25
|
作者
You, Sung Hyun [1 ]
Pak, Jung Min [1 ]
Ahn, Choon Ki [1 ]
Shi, Peng [2 ,3 ,4 ]
Lim, Myo Taeg [1 ]
机构
[1] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea
[2] Harbin Engn Univ, Coll Automat, Harbin 150001, Peoples R China
[3] Univ Adelaide, Sch Elect & Elect Engn, Adelaide, SA 5005, Australia
[4] Victoria Univ, Coll Engn & Sci, Melbourne, Vic 8001, Australia
基金
澳大利亚研究理事会; 新加坡国家研究基金会; 中国国家自然科学基金;
关键词
Digital phase-locked loop (DPLL); finite-memory structure; unbiasedness; FILTERS; ALGORITHM; NOISE; MODEL; L(2); PLL;
D O I
10.1109/TCSII.2016.2531138
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.
引用
收藏
页码:798 / 802
页数:5
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