An Agile and Wideband All-Digital SDR Receiver for 5G Wireless Communications

In this paper an original agile and wideband alldigital Software Defined Radio (SDR) receiver is presented. The analog-to-digital conversion is based on Pulse Width Modulation (PWM) and it is performed directly at the Radio Frequency (RF) stage. The system is implemented using the high speed differential input buffers of a medium range Field Programmable Gate Array (FPGA) as comparators to quantize the analog signal and generate the PWM representation. Simulation and measured results will be presented and evaluated in terms of Signal-to-Noise Ratio (SNR), Error Vector Magnitude (EVM), bandwidth and power efficiency. Briefly, this architecture allows an input bandwidth of almost 3GHz maintaining an EVM below 2,5% for a 4MHz signal.