Ultra-low Leakage ESD Protection Achieving 10.5 fA Leakage

This paper presents an electrostatic discharge (ESD) protection circuit and reviews best practices to interface a CMOS analog front-end (AFE) with off-chip high impedance (> 1 G Omega) and high precision (<1 pA resolution) current sensors. The proposed circuit uses an amplifier at the input/output (I/O) pin to drive the voltage across the ESD protection diodes to a near-zero value, thus enabling sub-pA leakage. Implemented in a 180 nm CMOS process, the proposed circuit reduces the leakage current by 7.5x (to <15 fA) compared to conventional techniques at 25 degrees C. The proposed circuit's resilience to ESD events was tested using the human-body model (HBM) standard and demonstrated similar ESD protection capabilities when compared to standard ESD protection circuits and improved protection over other low-leakage techniques. This technique achieves sub-pA leakage across the commercial temperature range (0 - 85 degrees C) while consuming just 15 mu W and 0.002 mm(2).